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Post-CTS Delay Insertion
Journal article   Open access   Peer reviewed

Post-CTS Delay Insertion

Jianchao Lu and Baris Taskin
VLSI design (Yverdon, Switzerland), v 2010
22 Feb 2010
DOI: https://doi.org/10.1155/2010/451809
url
https://doi.org/10.1155/2010/451809View
Published, Version of Record (VoR) Open

Abstract

A post-clock-tree-synthesis (post-CTS) optimization method is proposed that suggests delay insertion at the leaves of the clock tree in order to implement a limited version of clock skew scheduling. Delay insertion is limited on each clock tree branch simultaneous with a global monitoring of the total amount of delay insertion. The delay insertion for nonzero clock skew operation is performed only at the clock sinks in order to preserve the structure and the optimizations implemented in the clock tree synthesis stage. The methodology is implemented as a linear programming model amenable to two design objectives: fixing timing violations or optimizing the clock period. Experimental results show that the clock networks of the largest ISCAS'89 circuits can be corrected post-CTS to resolve the timing conflicts in approximately 90% of the circuits with minimal delay insertion (0.159 clock period per clock path on average). It is also shown that the majority of the clock period improvement achievable through unrestricted clock skew scheduling are obtained through very limited insertion (43% average improvement through 10% of max insertion).

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Computer Science, Hardware & Architecture
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