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Power Noise in TSV-Based 3-D Integrated Circuits
Journal article   Open access   Peer reviewed

Power Noise in TSV-Based 3-D Integrated Circuits

Ioannis Savidis, Selcuk Kose and Eby G. Friedman
IEEE journal of solid-state circuits, v 48(2), pp 587-597
01 Feb 2013
DOI: https://doi.org/10.1109/JSSC.2012.2217891
Featured in Collection :   UN Sustainable Development Goals @ Drexel
url
http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.300.5160View
SubmittedOpen Access (License Unspecified),  Open

Abstract

Engineering Engineering, Electrical & Electronic Science & Technology Technology
A three-dimensional (3-D) test circuit examining power grid noise in a 3-D integrated stack has been designed, fabricated, and tested. Fabrication and vertical bonding were performed by MIT Lincoln Laboratory for a 150 nm, three metal layer SOI process. Three wafers are vertically bonded to form a 3-D stack. Noise analysis of three power delivery topologies is described. Calibration circuits for a source follower sense circuit compare the different power delivery topologies as well as the separate 3-D stacked circuits. The effect of the through silicon via (TSV) density on the noise profile of a 3-D power delivery network is experimentally described. A comparison of the peak noise for each topology with and without board level decoupling capacitors, and resonant behavior is provided, and suggestions for enhancing the design of a 3-D power delivery network are offered.

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4 Record Views
15 citations in Web of Science
19 citations in Scopus

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UN Sustainable Development Goals (SDGs)

This publication has contributed to the advancement of the following goals:

#9 Industry, Innovation and Infrastructure

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Collaboration types
Domestic collaboration
Web of Science research areas
Engineering, Electrical & Electronic
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