Journal article
Pseudorandom testing for boundary-scan design with built-in self-test
IEEE design & test of computers, v 8(3), pp 58-65
Sep 1991
Abstract
The design of a pseudorandom pattern generator for a boundary-scan chip with built-in self-test is described. The proposed test-generation procedure, together with a method of connecting the generator outputs and the primary inputs of the chip under test, ensures full pattern coverage. The authors show how to evaluate the choice of generator parameters and initial states when there are more flip-flops in the generator than bits in the test pattern.< >
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Details
- Title
- Pseudorandom testing for boundary-scan design with built-in self-test
- Creators
- P Nagvajara - Drexel UniversityM.G KarpovskyL.B Levitin
- Publication Details
- IEEE design & test of computers, v 8(3), pp 58-65
- Publisher
- IEEE Computer Society
- Resource Type
- Journal article
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:A1991GB99900007
- Scopus ID
- 2-s2.0-0007449667
- Other Identifier
- 991019173543304721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Collaboration types
- Domestic collaboration
- Web of Science research areas
- Computer Science, Hardware & Architecture
- Engineering, Electrical & Electronic