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Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems
Journal article

Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems

Ragh Kuttappa, Baris Taskin, Scott Lerner and Vasil Pano
IEEE transactions on circuits and systems. I, Regular papers, v 68(4), pp 1636-1645
Apr 2021

Abstract

Capacitance Clocks low power multi-die systems Oscillators Resonant rotary clock Silicon Synchronization Topology VLSI Wires
This paper presents the integration of resonant clocking to multi-die architectures to synchronize individual chiplets connected through an active silicon interposer. The proposed inter-chiplet synchronization through the active silicon interposer rotary oscillator array (ASI-ROA) provides a unitary clock domain to the multiple die (i.e. multiple chiplets) in the package with a very low design overhead. System performance analysis is performed with parasitics-extracted, post-layout simulation models of two different sizes of representative heterogeneous multi-die architectures, each with varying number of RISC-V cores per die. Each RISC-V core of the multi-die package belongs to the unitary clock domain, designed with ASI-ROA to operate at a frequency of 2 GHz. The proposed architecture is investigated for robustness in frequency and skew across the multi-die system (MDS) with SPICE based simulations of post layout models, demonstrating variations of only 80 MHz for a 2 GHz target frequency. The power savings are upto 41% for the overall MDS, compared to an equivalent implementation with a contemporary ADPLL used to synchronize the multiple chiplets over the active interposer. The average clock skew of the completely resonant architecture presented in this work is 8.2 ps.

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Engineering, Electrical & Electronic
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