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SLECTS: Slew-Driven Clock Tree Synthesis
Journal article   Peer reviewed

SLECTS: Slew-Driven Clock Tree Synthesis

Weicheng Liu, Can Sitik, Emre Salman, Baris Taskin, Savithri Sundareswaran and Benjamin Huang
IEEE transactions on very large scale integration (VLSI) systems, v 27(4), pp 864-874
Apr 2019
DOI: https://doi.org/10.1109/TVLSI.2018.2888958

Abstract

Capacitance Clock networks Clocks computer-aided analysis Delays digital integrated circuits Integrated circuit interconnections integrated circuit synthesis low-power electronics Merging Microsoft Windows Wires
A slew-driven clock tree synthesis (SLECTS) methodology is proposed for nanoscale technologies where the interconnect resistance dominates device resistance, thereby increasing the challenge of satisfying the slew constraint. This issue is exacerbated at lower voltages due to degraded drive ability of the clock buffers. A paradigm shift from the traditional delay (and skew)-driven approaches to the proposed slew-driven methodology is therefore required. SLECTS is developed in this paper to satisfy tight slew constraints, which can be costly or infeasible with delay (skew)-driven methodologies and reduce the power dissipation of the clock tree, since the slew and skew constraints are simultaneously and methodically considered. Experimental results performed on an industrial circuit with more than 1M gates designed in 28-nm technology demonstrate that clock power is reduced by approximately 15% as compared to a commercial clock tree synthesis tool under similar slew and skew constraints.

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6 citations in Web of Science
12 citations in Scopus

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Collaboration types
Industry collaboration
Domestic collaboration
Web of Science research areas
Computer Science, Hardware & Architecture
Engineering, Electrical & Electronic
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