Journal article
Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis
IEEE transactions on very large scale integration (VLSI) systems, v 27(1), pp 1-10
Jan 2019
Abstract
Building clock trees for tight skew constraints of clock delivery networks is standard in the industry. Tight slew constraints of high-performance designs require post-processing techniques to satisfy slew constraints after clock tree synthesis (CTS). Post-processing adversely impacts the power dissipation. This paper proposes slew merging region CTS (SMRcts); a novel algorithm to satisfy bounded slew and skew constraints simultaneously during synthesis. Experimental results performed on International Symposium on Physical Design (ISPD) 2010 benchmarks using a 20-nm FinFET technology show an average reduction of 15% power over a bounded skew approach. Comparison to the ISPD 2010 CTS contest solutions in the literature shows SMRcts producing a 51% improvement in a utility metric. Scalability of SMRcts is demonstrated on ISPD 2013 benchmarks with up to 100k sinks.
Metrics
Details
- Title
- Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis
- Creators
- Scott Lerner - Drexel UniversityBaris Taskin - Drexel University
- Publication Details
- IEEE transactions on very large scale integration (VLSI) systems, v 27(1), pp 1-10
- Publisher
- IEEE
- Grant note
- DGE-1656737 / National Science Foundation (10.13039/100000001)
- Resource Type
- Journal article
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000455117600001
- Scopus ID
- 2-s2.0-85055718745
- Other Identifier
- 991019168877804721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Web of Science research areas
- Computer Science, Hardware & Architecture
- Engineering, Electrical & Electronic