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The Adiabatically Driven StrongARM Comparator
Journal article   Open access

The Adiabatically Driven StrongARM Comparator

Leo Filippini and Baris Taskin
IEEE transactions on circuits and systems. II, Express briefs, v 66(12), pp 1957-1961
Dec 2019
DOI: https://doi.org/10.1109/TCSII.2019.2896597
url
https://doi.org/10.1109/tcsii.2019.2896597View
Accepted (AM)Open Access (Publisher-Specific),  Open

Abstract

ADC Adiabatic adiabatic comparator adiabatic logic Capacitance charge recovery circuits charge recovery comparator charge recovery logic Circuits and systems Clocks Comparator Discharges (electric) Energy consumption Transistors
Adiabatic logic, also known as charge recovery logic, is subject to active research in the field of low-energy computation. Although the principles of adiabatic operation are well understood in digital circuits, analog and mixed-signal circuit implementations are largely unexplored. This brief shows that the strongARM comparator can take advantage of adiabatic principles by: 1) being powered by a sine-wave, the power-clock, rather than the conventional dc power supply, V DD and 2) using an adiabatic buffer as the output stage, rather than an SR-latch. Post-layout simulations in a 65-nm technology show that the adiabatically driven strongARM has similar characteristics to the traditional strongARM: +2% noise, +0.1% input offset voltage, and the same regeneration time-constant, while only consuming between 28% and 55% of the energy of the traditional strongARM, in the typical case.

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Engineering, Electrical & Electronic
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