Journal article
Vertical Arbitration-Free 3-D NoCs
IEEE transactions on computer-aided design of integrated circuits and systems, Vol.37(9), pp.1853-1866
Sep 2018
Abstract
The vertical interlayer communication channel plays a critical role in defining the performance of a 3-D network-on-chip (NoC). In this paper, an arbitration-free design for the shared vertical channels is proposed. The proposed vertical arbitration-free 3-D NoC is compared with other 3-D NoC architectures using traditional synthetic traffic patterns and Rentian traffic emulating applications for chip multiprocessors. The results of the analysis show comparable performance in throughput, energy, and latency compared to a symmetric 3-D NoC with savings up to \approx { 20\%} in area. The proposed NoC is superior in performance to a 3-D NoC utilizing vertical arbitration with a similar area footprint.
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Details
- Title
- Vertical Arbitration-Free 3-D NoCs
- Creators
- Ankit More - IntelVasil Pano - Drexel UniversityBaris Taskin - Drexel University
- Publication Details
- IEEE transactions on computer-aided design of integrated circuits and systems, Vol.37(9), pp.1853-1866
- Publisher
- IEEE
- Grant note
- NSF ECCS-1232164 / Division of Electrical, Communications and Cyber Systems (10.13039/100000148) NSF CNS-1305350 / Division of Computer and Network Systems (10.13039/100000144)
- Resource Type
- Journal article
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Identifiers
- 991019167646004721
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