Logo image
Back
Vertical Arbitration-Free 3-D NoCs
Journal article   Open access   Peer reviewed

Vertical Arbitration-Free 3-D NoCs

Ankit More, Vasil Pano and Baris Taskin
IEEE transactions on computer-aided design of integrated circuits and systems, v 37(9), pp 1853-1866
Sep 2018
DOI: https://doi.org/10.1109/TCAD.2017.2768415
url
https://doi.org/10.1109/tcad.2017.2768415View
Accepted (AM)Open Access (Publisher-Specific),  Open

Abstract

3-D integrated circuits (ICs) multicore design Multicore processing Multiprocessing systems Network-on-chip network-on-chip (NoC) routing on-chip networks Performance evaluation Routing protocols Telecommunication traffic Through-silicon vias
The vertical interlayer communication channel plays a critical role in defining the performance of a 3-D network-on-chip (NoC). In this paper, an arbitration-free design for the shared vertical channels is proposed. The proposed vertical arbitration-free 3-D NoC is compared with other 3-D NoC architectures using traditional synthetic traffic patterns and Rentian traffic emulating applications for chip multiprocessors. The results of the analysis show comparable performance in throughput, energy, and latency compared to a symmetric 3-D NoC with savings up to \approx { 20\%} in area. The proposed NoC is superior in performance to a 3-D NoC utilizing vertical arbitration with a similar area footprint.

Metrics

10 Record Views
2 citations in Web of Science
3 citations in Scopus

Details

InCites Highlights

Data related to this publication, from InCites Benchmarking & Analytics tool:

Collaboration types
Industry collaboration
Domestic collaboration
Web of Science research areas
Computer Science, Hardware & Architecture
Computer Science, Interdisciplinary Applications
Engineering, Electrical & Electronic
Logo image