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Wafer map pattern recognition using ternary spiking neural networks
Journal article - Supervised student publication   Open access   Peer reviewed

Wafer map pattern recognition using ternary spiking neural networks

Abhishek Kumar Mishra, Anup Kumar Das and Nagarajan Kandasamy
Microprocessors and Microsystems, v 123, Forthcoming
15 Jun 2026
DOI: https://doi.org/10.1016/j.micpro.2026.105299
Featured in Collection :   Research Supported by Drexel Libraries' OA Programs
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https://doi.org/10.1016/j.micpro.2026.105299View
Published, Version of Record (VoR) Open Access via Drexel Libraries Read and Publish Program 2026 Open CC BY V4.0

Abstract

Semiconductor device testing Wafer map defects Spiking neural networks
The analysis of wafer map patterns is crucial for detecting manufacturing defects in integrated circuits. Although deep neural networks have been used for this task, spiking neural networks (SNNs) offer a more energy-efficient alternative by using spike activations, replacing multiplications with simpler additions. We develop an SNN with ternary spiking neuron model that outputs values of instead of the traditional , to enhance the neuron’s information capacity and learning. It also improves the model’s control over the influence of each type of spike on the membrane potential, helping to prevent excessive activation and maintain stability by balancing excitatory and inhibitory signals. Using direct spike training with pseudogradients, our model outperforms both binary SNNs and DNNs on the WM-811k wafer benchmark dataset, excelling in identifying critical defect patterns that are underrepresented in the dataset with high accuracy and computational efficiency.

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