Preprint
Mapping and Scheduling Spiking Neural Networks On Segmented Ladder Bus Architectures
12 Jun 2025
Abstract
Large-scale neuromorphic architectures consist of computing tiles that
communicate spikes using a shared interconnect. The communication patterns in
these systems are inherently sparse, asynchronous, and localized, as neural
activity is characterized by temporal sparsity with occasional bursts of high
traffic. These characteristics require optimized interconnects to handle
high-activity bursts while consuming minimal power during idle periods. Among
the proposed interconnect solutions, the dynamic segmented bus has gained
attention due to its structural simplicity, scalability, and energy efficiency.
Since the benefits of a dynamic segmented bus stem from its simplicity, it is
essential to develop a streamlined control plane that can scale efficiently
with the network. In this paper, we present a design methodology for a
scenario-aware control plane tailored to a segmented ladder bus, with the aim
of minimizing control overhead and optimizing energy and area utilization. We
evaluated our approach using a combination of FPGA implementation and software
simulation to assess scalability. The results demonstrated that our design
process effectively reduces the control plane's area footprint compared to the
data plane while maintaining scalability with network size.
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Details
- Title
- Mapping and Scheduling Spiking Neural Networks On Segmented Ladder Bus Architectures
- Creators
- Phu Khanh HuynhFrancky CatthoorAnup Das
- Resource Type
- Preprint
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Other Identifier
- 991022058463404721